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Using FPGA as interface chip to realize data access from DSP to SDRAM

Author: Release time:2020-04-08 Source: Font: Big Middle Small View count:119

In the DSP application system, the situation of requiring a large amount of external expansion memory is often encountered. For example, in digital cameras and video cameras, in order to temporarily store many pictures or images taken on the spot, the data processed by the DSP needs to be transferred to external storage for later use. From the current memory market, SDRAM is favored by DSP developers because of its advantages in performance and price. Direct interface between DSP and SDRAM is impossible.

FPGA (Field Programmable Gate Array) is more and more used in field circuit design because of its flexible use, fast execution speed, and rich development tools. This article uses FPGA as an interface chip to provide control signals and timing signals to achieve data access from DSP to SDRAM.

1. Introduction of SDRAM

The SDRAM used in this article is TMS626812A, and Figure 1 is its functional block diagram. It is divided into two internally, each 1M bytes, the data width is 8 bits, so the total storage capacity is 2M bytes.

All input and output operations are carried out under the effect of the rising edge of the clock CLK, and the refresh clock alternately refreshes the internal two RAMs. TMS626812A mainly has six control commands, they are: bar exciting tip / row address entry, column address entry / write operation, column address entry / read operation, bar invalidation, auto refresh, auto refresh The commands used in the interface between SDRAM and TMS320C54x are: MRS, DEAC, ACTV, WRT-P, READ-P and REFR. Here, the design goal is to generate control signals to meet the timing requirements of these commands. For specific instructions on TMS626812A, you can check its data sheet.

2. General interface between SDRAM and TMS320C54x

Figure 2 is a general interface block diagram of DSP and SDRAM. In the figure, DSP I / F stands for TMS320C54x terminal interface unit, and SDRAM CNTL stands for SDRAM terminal interface control unit. SDRAM is set to read and write 128 bytes at a time, while DSP only reads and writes one byte at a time, so two buffers B0 and B1 are established to buffer and transfer data. Both B0 and B1 are 128 bytes in size and are mapped to the same address space in the DSP.

Figure 2 SDRAM and DSP general interface block diagram

Although B0 and B1 correspond to the same address space, the two buffers cannot be legally accessed at the same time. In fact, when B0 is accessed by DSP, B1 is accessed by SDRAM, and vice versa. If the DSP writes data to B1, SDRAM reads the data from B0; and when the SDRAM data is written to B0, the DSP reads the data from B1. Both reading or writing from the same buffer at the same time will trigger an error. The data transfer method described above has two benefits: one is to accelerate the access speed of TMS320C54x, and the other is to solve the problem of clock asynchronization between the two.

3. Hardware design in FPGA

TMS320C54x provides the following signals for the expansion of external memory: CLK, CS, AO ~ A15, D0 ~ D15, RW, MATRB, ISTRB, IS, and SDRAM receives the following signals: CLK, CKE, CS, CQM, W, RAS, CAS 、 A0 ~ A11。 Due to the different control signals at both ends, it is necessary to add control logic between DSP and SDRAM in order to interpret the signal from DSP into the signal that SDRAM can receive. Figure 3 is the top-level hardware interface diagram designed with FPGA.

The figure is mainly composed of three modules: DSP-IQ, DMA-BUF and SD-CMD. Among them DSP-IO is the interface of DSP end, used for decoding SDRAM address and order sent by TMS320C54x. DMA-BUF stands for buffers BO, B1. The SD_CMD module is used to generate various signals required for SDRAM access.

The DSP_IO module includes IO_DMA, DSP_BUF, and DSP_READ. IO_DMA generates SDRAM command signals, that is, DSP_RDY, DSP_SD_RW, DSP_SD_BANK_SW, DSP_SD_ADDR [20..0], DSP_SD_ADDR_RESET, DSP_SD_START in Figure 3. DSP_BUF generates the address, data and control signals to access B0 and B1. In Figure 3, it refers to DSP_SD_BUFCLKI, DSP_SD_BUFCLKO, DSP_SD_BUFWE, DSP_SD_BUFADDR [6..0], DSP_SD_BUFIN [7..0]. The DSP-READ sub-module is used to control the reading and writing direction of the DSP.

DMA_BUF is divided into two buffers, B0 and B1, for data transfer. The input and output signals of each buffer include: CLKI, CLKO, WE, ADDR [6-0], DATA_IN [7-0], DATA_OUT [7 -0]. BANK_SW is a switch signal used for DSP and SDRAM to switch access to B0 and B1.

The SD_CMD module includes refresh, read, and write functions. When the DSP chip issues an SDRAM read command, 128 bytes of data are read from the SDRAM and stored in B0 or B1. When the DSP issues a write command, the 128 bytes of data are transferred to B0 or B1 and are Finally write to SDRAM.

4. Software design

TMS626812A SDRAM has a storage capacity of two megabytes. So the DSP uses two I / O addresses to transfer the high and low addresses of the SDRAM to the FPGA. In this article, the two I / O address pairs apply 03h (DMA_ADDH) and 04h (DMA_ADDL) in Figure 4. In addition, there is an I / O address (05h in Figure 4) used to send commands to the FPGA to generate SDRAM access signals.

The operation steps when DSP writes data to SDRAM are as follows:

(1) The data is written to B0 or B1 first.

(2) The access address of SDRAM is sent to the FPGA via the I / O addresses DMA_ADDH and DMA_ADDL of the DSP.

(3) The DSP sends a command (I / O address is DMA_CTL) to the FPGA to generate a control signal, so that the SDRAM reads the value from B0 or B1.

The operation steps of DSP reading data from SDRAM are as follows:

(1) The DSP transmits the address to access the SDRAM.

(2) The DSP transmits a command via the FPGA, so that the data is read from the SDRAM to the FPGA.

(3) The DSP reads the data from B0 or B1.

The specific design should be supplemented with reference to relevant materials. When different DSPs and different types of SDRAM interfaces, there will be subtle differences. After the circuit design is completed, careful and multifaceted tests are required.

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