The importance of memory chips is becoming more and more prominent today. Whether it's a PC or a cell phone, a tablet or a game console, there are memory chips everywhere. However, there is often a difference in the memory used in different products. In addition to our common DDR and GDDR, there is also a dedicated low-power memory in mobile devices, that is LPDD.
Today, this article will walk with you closer to LPDDR memory, to explore the past, present and future of this special memory for the low-power market.
LPDDR is a memory product widely used in mobile devices and low-power devices, and the full name of LPDDR is Low-Power DDRSDRAM. Compared to common DDR memory, LPDDR is characterized by "LP", which means low power consumption.
Therefore it is widely used in power sensitive applications including cell phones, tablet PCs, and low power devices. In addition to power consumption, LPDDR has also made a series of adaptable improvements compared to DDR in terms of chip area, bit width, voltage, frequency, prefetching, and bus settings to better meet the needs of low-power device applications.
When mobile computing devices first emerged, it was realized that DDR memory for desktop use had many problems when used in mobile devices, including excessive chip area, higher voltage resulting in higher power consumption.
Therefore, Samsung, Micron, Intel, Nvidia and other manufacturers have joined forces to launch a new memory technology specification that has a lower voltage of 1.8V, compared to DDR memory which has a voltage of up to 2.5V.
On the technical side, considering the sensitivity of mobile devices to energy consumption, the new products incorporate energy-saving features such as DeepPower Down Mode (for hibernation to significantly reduce power consumption), configurable self-refresh and temperature-compensated self-refresh (to reduce the number of refreshes and thus reduce power consumption), making the new products relatively DDR in terms of power consumption. The new product has a relatively large drop in power consumption compared to DDR.
In addition, the data bit width, the traditional DDR data bit width is 64bit, and taking into account the weak computing power of mobile devices, too much data bus bandwidth does not make sense and occupy too much wiring area, so this new storage products will be 10 interface bit width reduced to 32bit (manufacturers can configure 16bit or even 8bit use as needed), which also largely reduces the power consumption of the product.
With the new low voltage, small size and new energy saving technology, this new memory particle is called LPDDR or mDDR in order to distinguish it from traditional DDR. However, there is no unified specification for LPDDR in the early days, and the first mobile products using LPDDR memory include the famous iPhone 3 series phones, Samsung Galaxy series The first mobile products that used LPDDR memory included the famous iPhone3 series phones, Samsung Galaxy series phones and tablet PCs, etc.
In terms of product models, the first generation of LPDDR included LPDDR 400 and LPDDR 533 (the latter was also known as LPDDRe, with e meaning "enhance"). As the basic specification is derived from DDR, LPDDR prefixed value is also 2n, internal clock frequency is 200MHz-266MHz, 10 frequency is the same as 200MHz-266MHz, data transfer rate is 400MT/s-533MT/s, data bandwidth under 32bit line can reach 1.6GB/s-2.1GB/s, also can fully meet the mobile devices at that time for bandwidth needs of mobile devices at that time.
The new LPDDR brought a whole new market, and this market gained rapid development. In order to regulate the products and market behavior, JEDEC also launched the specification JESD209B for LPDDR at the end of 2008, after which LPDDR was incorporated into the standard management by JEDEC, thus becoming a unified standard for the industry.
JEDEC introduced the new LPDDR2 specification JESD209-2F in April 2009, which expands the LPDDR2 product range to include non-volatile memory, and also brings higher memory density, better performance, further reduced package size, and a number of power reduction technologies.
According to the specification, LPDDR2 is actually divided into three products, LPDDR2-S2, LPDDR2-S4 and LPDDR2-N. The first two of them are traditional volatile storage devices, and the last one, LPDDR2-N, is a non-volatile storage device.
This kind of memory chip is often used in special occasions, such as some IoT devices and industrial devices that perform a single function and have a relatively small amount of tasks and calculations, such as smart meters and industrial computers.
In terms of product models, accordingly, the data transfer rate of LPDDR2 is increased to 800M T/s and 1066M T/s, and the bandwidth at 32bit (optional 16bit solution, bandwidth halved) is also increased to 3.2GB/s and 4.2G B/s, doubling compared to the previous generation of LPDDR.
The life cycle of LPDDR2 is longer.
LPDDR3 focuses its improvements on data transfer rates and bandwidth, while also making some optimizations while retaining LPDDR2 power control features.
In addition, in terms of packaging, LPDDR3 begins to support POP packaging or discrete packaging, the former of which is very important, POP stacking type of packaging to further reduce the area inside the mobile device to lay the foundation.
LPDDR3 with a very large number of products, including the famous Apple iPhone 5s, Macbook Air, Samsung Nexus 10 and Microsoft Surface Pr03. late Qualcomm launched Snapdragon 800 and Snapdragon 600 also provide support for LPDDR3.
With the further development of mobile computing, LPDDR3 continues to improve according to the previous technical route of development began to meet the market demand, especially in HD video, HD photography and other functions gradually mature, mobile devices put forward extremely high requirements for memory bandwidth, which is the previous LPDDR3 and its related architecture is difficult to do. Therefore, JEDEC needs a new architecture to meet the needs of mobile computing and to continue to balance power consumption and bandwidth.
This is LPDDR4, which brings several major improvements over LPDDR3.
First is the minimum operating voltage from the previous 1.2v further reduced to l.lv, the continuous reduction of voltage brings energy consumption reduction.
Second, LPDDR4 switched to 16n prefetch, by doubling the prefetch value, LPDDR4 can increase bandwidth without continuing to increase the internal clock frequency.
Third, the internal bus of LPDDR4 has been changed from 32bit to 2 16bit, and the total bandwidth is still 32bit. This improvement makes the internal data access efficiency increase significantly and reduces the power consumption of the storage part to some extent.
In addition to the above three important improvements, LPDDR4 CA bus from the previous 10-bit DDR command (inherited from the LPDDR2 era) to a 6-bit SDR bus, but the addition of multi-cycle command function, as the new bus only in the upper or lower edge of the data transfer information and bit width is narrower, lower energy consumption, some other improvements include a dedicated command to start the self-refreshing Other improvements include self-refresh by dedicated command, further reduction in package size, increased data density, etc.
After the brilliance brought by LPDDR4X, LPDDR5 is also starting to prepare in earnest. 2019, JEDEC released the JESD209-5 specification, officially bringing the LPDDR5 standard.
From an architectural point of view, LPDDR5 retains the 16n prefetch value used in the LPDDR4 era, but adds the Bank Group concept used on desktop DDR4.
Simply put, if the previous LPDDR memory had 8 or 16 internal blocks, they were read and written in a serial fashion, with block O being read and written and then read and written to block 1, block 2, and so on. Therefore LPDDR5 can significantly increase the data bandwidth without increasing the prefetch value and frequency, relying only on the block group and 10 parts of the frequency increase.
In addition to the introduction of the block group concept, LPDDR5 also brings including a new scalable clock architecture that solves the problem of the CA bus speed not being able to keep up with the data bus speed increase.
From the introduction of this article can be seen, LPDDR in the development process, from off the DDR to embark on the route of independent development, and now LPDDR5 bandwidth gradually catch up with the desktop platform, while power consumption is constantly reduced, can be described as out of a high-performance, low-power independent road.
For mobile devices and low-power devices, LPDDR's high bandwidth and low power consumption characteristics are very satisfactory. The future of LPDDR memory will continue to develop on this path, bringing us more lightweight, energy-efficient but high-speed products.
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