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C-debut, Intel released new tools

Author: Release time:2019-07-11 Source: Font: Big Middle Small View count:62

At this week's SEMICON West conference in San Francisco, Intel's engineering experts introduced the latest information on Intel's advanced packaging technology and introduced a new set of basic tools, including innovative applications that combine EMIB and Foveros technology. New Omni-Directional Interconnect (ODI) technology. Intel's new packaging technology will be combined with its world-class process technology to help customers unleash their creativity and move toward a new era of computing.

Babak Sabi, vice president and general manager of package testing technology development at Intel Corporation, said: "Our vision is to use advanced technology to package chips and small chips together to achieve the performance of single-chip system-on-chip. Heterogeneous integration technology for us Chip architects offer unprecedented flexibility to mix IP and process technologies with different memory and I/O units in new, diverse modules. Intel's vertically integrated architecture is in the era of heterogeneous integration Unique, it gives us unparalleled power to optimize the architecture, process and packaging to deliver leading products."


Chip packaging seems to be inconspicuous in the electronics supply chain, but it has always played a key role. As a physical interface between the processor and the motherboard, the package provides a landing zone for the chip's electrical signals and power. As the electronics industry moves toward a data-centric era, advanced packaging will play a bigger role than in the past.

Packaging is not just the last step in the manufacturing process, it is becoming a catalyst for product innovation. Advanced packaging technology integrates the computational engine of multiple process technologies to achieve performance similar to single-chip, but its platform range far exceeds the wafer size limitations of single-chip integration. These technologies will greatly improve product-level performance and efficiency, reduce area, and fully transform the system architecture.

As a leader in advanced packaging technology, Intel is able to offer both 2D and 3D packaging technologies. At the SEMICON West conference, Intel shared three new technologies that will open a new dimension to the chip product architecture.

Co-EMIB: Intel's EMIB (Embedded Multi-Chip Interconnect Bridge) 2D package and Foveros 3D package technology utilize high-density interconnect technology to achieve high bandwidth, low power consumption and achieve a very competitive I/O density . Intel's new Co-EMIB technology connects higher computing performance and capabilities. Co-EMIB enables two or more Foveros components to be interconnected, essentially achieving single-chip performance. Designers are also able to connect simulators, memory and other modules with very high bandwidth and very low power consumption. (Co-EMIB Technology Video)

ODI: Intel's new Omni-directional Interconnect Technology (ODI) provides greater flexibility in the full range of interconnected communications between small and medium-sized chips. The top chip can communicate horizontally with other small chips like EMIB technology, and can communicate vertically with the underlying die via through-silicon vias (TSVs), just like Foveros technology. ODI utilizes large vertical vias to power directly from the package substrate to the top die. This large via is much larger than conventional through-silicon vias and has lower resistance, which provides more stable power transfer while achieving more stacking. High bandwidth and lower latency. At the same time, this approach reduces the number of through silicon vias required in the base wafer, frees up more area for active transistors, and optimizes die size. (ODI Technology Video)

MDIO: Based on its Advanced Interface Bus (AIB) physical layer interconnect technology, Intel has released a new inter-die interface technology called MDIO. MDIO technology supports modular system design for small chip IP block libraries, providing higher energy efficiency and achieving more than twice the response speed and bandwidth density of AIB technology.

These new technologies have combined to expand Intel's powerful toolbox. They will be combined with Intel's process technology to become a creative palette for chip architects, allowing them to freely design innovative products.

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