Shopping Cart 0

Your shopping cart is empty! Please select the model you want to purchase first.
Product Name Manufacturer Unit Price Quantity Total
Quantity: 0 Total: $0.0

How to quickly and easily implement an embedded FPGA

Author: Release time:2020-01-13 Source: Font: Big Middle Small View count:13

Embedded FPGAs are no longer a dream. According to Achronix, in the future, chip designers will simply add wire-to-wire interconnects to their SoC designs.

Steve Mensor, vice president of marketing for Achronix Semiconductor, said that this embedded FPGA (eFPGA) IP product called Speedcore is now ready and shipping. Although it did not disclose shipment numbers and customer names, the company said the product is now available to customers.

Speedcore symbolizes the company's first foray into the IP business. Achronix has been producing its flagship FPGA product, the Speedster 22i, since 2013. So for Achronix, this is a long way to go because the company first announced plans to develop eFPGA IP only four years ago.

Nevertheless, Achronix sees a glimmer of light here, and is expected to make its first profit this year, with revenue of $ 12 million. According to Mensor, the company expects its sales to grow by more than $ 40 million in 2017, further making the eFPGA IP business an "important driver" of Achronix's growth.

Design Tools

Speedcore uses the same high-performance architecture as the Achronix Speedster 22i FPGA. Designed for computing and network acceleration applications, Speedcore eFPGA IP will be integrated into other companies' ASICs for data centers, wireless infrastructure and network equipment.

According to Mensor, the biggest advantage of eFPGA is its design tools. Over the years, Achronix has learned that customers need better design tools to bring them quality results, ease of use, and third-party integration, all of which are part of the Achronix CAD Environment (ACE). Serving.

In order to be part of the system, the eFPGA IP must have a functional design that can be easily integrated into the SoC. Achronix offers GDS II Edition Speedcore IP that allows customers to integrate directly into their SoCs, as well as custom versions of ACE tools that allow customers to design, verify, and program Speedcore eFPGA functions.

CPU casting?

The entire electronics industry knows that FPGAs are extremely popular. Just look at Microsoft's Project Catapult.

Microsoft explained that this program is specifically designed to "accelerate Microsoft's supercomputing foundation in networking, security, cloud services, and artificial intelligence (AI), etc." The biggest sights of technologies-including GPUs, FPGAs and ASICs.

The key to Microsoft's Project Catapult is the Altera Stratix V D5 FPGA. Mensor emphasized that the prevailing perception across the electronics industry is that Microsoft's plan led to Intel's decision to acquire Altera.

With AlphaGo, Googler's custom Tensor processor unit has also inspired many engineers to start thinking about everything from ASICs to GPUs and DSPs. Mensor explained that they are looking for technologies that can handle "accelerated unstructured search, machine learning, and artificial intelligence" more efficiently.

FPGA application areas and growth stages

FPGAs have been popular on the market as "glue chips" since the mid-1990s, and are now redefining their value as coprocessors for CPUs. In this role, FPGAs can accelerate encryption / decryption, compression / decompression, or even preprocessing data packets so that only relevant shared data can be transmitted and processed.

The FPGA's parallel environment has proven to be very effective when performing unstructured searches. For example, compared to CPUs that are designed to divide functions into smaller parts and work sequentially, FPGAs can complete the entire task in a single frequency cycle in parallel.

When the wireless infrastructure must cover multiple geographic regions, FPGAs are a backup trump card for programmable digital front ends and geographic region customization.

Wiring between chips

Although embedding FPGAs in SoCs always brings good design ideas to designers, it is not easy for FPGA vendors to realize this desire.

"It's very difficult to route between different chips," Mensor said. The key to successful eFPGA IP integration is to minimize latency and maximize throughput. The company emphasized that Achronix was the first to offer high-density FPGAs with embedded system-level IP.

For companies that "want to combine all the efficiency of ASIC design with the flexibility of eFPGA programmable hardware accelerators on the same chip," Achronix offers them the same eFPGA technology.

For IP vendors, integration is very challenging because customers always have different ideas and methods for optimizing chip size, power consumption and resource allocation for specific applications. They also defined the number of lookup tables, the number of embedded memory modules, and the number of DSP modules.

But the problem is not necessarily the customer's different implementation methods, but they often use different methods for chip testing and verification. Mensor explained that customers don't know how IP vendor tools work with them. For example, "We often hear customers asking:‘ How can I turn off the timing with your IP? '”

Although Achronix does not integrate its IP for customers, its business depends on whether the tools provided are sufficient for customers to complete their designs quickly.

Achronix NT31P1 Achronix also acquired a number of third-party IP, including interface protocols, programmable IO, SerDes, and PLL. So was Achronix having trouble developing FPGAs and meeting customer needs? Mensor said, "We always try to turn every problem we encounter into an opportunity."

For Achronix, the key was to integrate the company's FPGA architecture. The end result is a more streamlined Speedster 22i with less space occupied by programmable IO, SerDes, and interface controllers. In contrast, rival high-end FPGAs typically use approximately 50% of the chip area.

general purpose FPGA

Achronix NT31P2 FPGA chip size comparison

Increase latency and transfer rates

Achronix believes that a Speedcore eFPGA capable of wire-to-wire connection to an SoC can help eliminate a large number of programmable IO buffers, thereby reducing power consumption by half. In addition, Speedcore's chip size is also smaller than standard FPGAs, enabling eFPGA costs to be reduced by more than 90%.

However, Mensor emphasized that "for most customers, the biggest determinants are latency and throughput issues." According to Achronix, eFPGA has higher interface performance than a stand-alone FPGA, which is expected to increase 10 times Throughput and latency performance.

Speedcore can now use TSMC 16FF + process and develop with TSMC 7nm technology. The company also promises that Achronix's modular architecture will make it easy to transfer this technology to different process technologies and stacks.

Hot News